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representational state transfer : ウィキペディア英語版
representational state transfer

In computing, representational state transfer (REST) is the software architectural style of the World Wide Web. REST gives a coordinated set of constraints to the design of components in a distributed hypermedia system that can lead to a higher-performing and more maintainable architecture.
To the extent that systems conform to the constraints of REST they can be called RESTful. RESTful systems typically, but not always, communicate over Hypertext Transfer Protocol (HTTP) with the same HTTP verbs (GET, POST, PUT, DELETE, etc.) which web browsers use to retrieve web pages and to send data to remote servers.〔 REST interfaces with external systems using resources identified by Uniform Resource Identifier (URI), for example /people/tom, which can be operated upon using standard verbs, such as DELETE /people/tom.
REST was initially proposed by Roy Thomas Fielding in his 2000 PhD dissertation "Architectural Styles and the Design of Network-based Software Architectures".〔
〕 Fielding developed the REST architectural style in parallel with HTTP 1.1 of 1996-1999, based on the existing design of HTTP 1.0〔
(【引用サイトリンク】title= Fielding discusses the development of the REST style )

of 1996.
==Architectural properties==
The architectural properties affected by the constraints of the REST architectural style are:〔〔
* Performance - component interactions can be the dominant factor in user-perceived performance and network efficiency.〔

* Scalability to support large numbers of components and interactions among components. Roy Fielding, one of the principal authors of the HTTP specification, describes REST's effect on scalability thus:
:
* Simplicity of interfaces
* Modifiability of components to meet changing needs (even while the application is running)
* Visibility of communication between components by service agents
* Portability of components by moving program code with the data
* Reliability is the resistance to failure at the system level in the presence of failures within components, connectors, or data〔

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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